In a vertical MOSFET with an inverting trench gate structure, a gate voltage is applied to a gate electrode formed within a trench to define a channel in a p-type base region located on a trench side, and performs operation of allowing a current to flow between a drain and a source through the channel. In the vertical MOSFET of this type, an impurity concentration dependence in a p-type base region on an on-resistance and an element breakdown voltage is large. In other words, when an impurity concentration in a p-type base region is lowered, a channel mobility can be increased, a channel resistance is reduced, and the on-resistance is reduced. On the other hand, a breakdown voltage between the drain and the source is lowered due to a punch-through phenomenon to decrease the element breakdown voltage. For that reason, it is essentially difficult to perform both of the realization of a high channel mobility and the securement of the element breakdown voltage.
In order to solve the above problem, Patent Literature 1 has proposed an SiC semiconductor device in which a low-concentration n-type thin film layer is formed over an overall side surface of a trench in a vertical MOSFET having a trench gate structure. In the SiC semiconductor device, an n− type drift layer and a p-type base region are formed in order on an n+ type substrate as a semiconductor substrate. An n+ type source region is formed in a surface layer portion of the p-type base region, and a trench is defined to penetrate through the n+ type source region and the p-type base region. An n-type thin film layer is provided on a side surface of the trench, and a gate electrode is provided on a surface of the n-type thin film layer through a gate insulating film. A source electrode electrically connected to the n+ type source region is provided on a front surface side of the semiconductor substrate, and a drain electrode electrically connected to the n+ type substrate is provided on a rear surface side of the semiconductor substrate. Thus, a vertical MOSFET with a trench gate structure is configured.
In the SiC semiconductor device configured as described above, a channel is defined in the n-type thin film layer, and a current flows between the drain and the source through the n-type thin film layer. Therefore, because the channel mobility can be set on the basis of the impurity concentration of the n-type thin film layer, the channel mobility is increased to reduce the on-resistance. Because the impurity concentration in the p-type base region can be set without taking the channel mobility into consideration, the element breakdown voltage can be also ensured.
However, in the vertical MOSFET with the trench gate structure disclosed in the above-mentioned Patent Literature 1, such a problem that the self-turn-on occurs when noise enters the gate electrode in association with a reduction in a threshold voltage determined by the impurity concentration of the n-type thin film layer occurs.